electronic-lab May 2012

electronic-lab@lists.fedoraproject.org

5 participants
8 discussions

Fwd: update for EPEL6 to ghc-7.0.4 in testing
by Shakthi Kannan 27 May '12

27 May '12

FYI! The electronic lab packages that use Haskell will now be available for EPEL-6. SK ---------- Forwarded message ---------- From: Jens Petersen <petersen(a)redhat.com> Date: Mon, May 28, 2012 at 9:09 AM Subject: update for EPEL6 to ghc-7.0.4 in testing To: Fedora Haskell discussion list <haskell(a)lists.fedoraproject.org> Hi, I am pleased to announce a refresh of the Haskell packages for EPEL-6 is now available in testing. The major changes are: - ghc-6.12.3 -> ghc-7.0.4 - Haskell Platform updated to 2011.4 - xmonad updated to 0.10 - darcs updated to 2.5.2 - gtk2hs packages to 0.12.2 [1] If you use EPEL6 then please test. https://admin.fedoraproject.org/updates/FEDORA-EPEL-2012-5980/ghc-7.0.4-46.… Thanks, Jens [1] note that gtksourceview2 doesn't build with the gtksourceview2 in el6 though. _______________________________________________ haskell mailing list haskell(a)lists.fedoraproject.org https://admin.fedoraproject.org/mailman/listinfo/haskell -- Shakthi Kannan http://www.shakthimaan.com

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asimut: Getting a ?u in the output pattern with structural simulation
by Ashwith Rego 20 May '12

20 May '12

Hi, I have the following code for an inverter: ============================ --inverter (NOT) gate entity invg is port ( a : in bit; x : out bit; vdd : in bit; vss : in bit ); end invg; architecture vbe of invg is begin x <= not (a); end vbe; ============================ I saved this in invg.vbe Next I ran the following commands: boom -l 3 -d invg boog invg_o invg -x 1 -m 2 This resulted in the file invg.vst which contains the following: ============================ entity invg is port ( a : in bit; x : out bit; vdd : in bit; vss : in bit ); end invg; architecture structural of invg is Component inv_x2 port ( i : in bit; nq : out bit; vdd : in bit; vss : in bit ); end component; begin x_ins : inv_x2 port map ( i => a, nq => x, vdd => vdd, vss => vss ); end structural; ============================ I now created a pattern to drive the input. However I see a ?u in the output. I ran the following command asimut invg invg invg_out I do not see this problem when I run behavioral simulations. The output patterns file is as below. The input file contains ?* instead of the ?u ============================ -- description generated by Pat driver -- date : Sun May 20 14:50:49 2012 -- revision : v109 -- sequence : invg -- input / output list : in vdd B; in vss B; in a B; out x B; begin -- Pattern description : -- vva x -- ds -- ds : 100?u; : 101?u; end; ============================ Is there something I'm doing wrong that is causing the output to show as undefined? The code is from this e-book which I am using to learn about the alliance package: http://www.cc.toin.ac.jp/sc/palacios/openbook/vlsie.pdf (1.8MB) Thanks, Ashwith J. Rego ----------------- My Webpage: http://ashwith.wordpress.com/ Find me on LinkedIn at: http://www.linkedin.com/in/ashwith Follow Me on Twitter at: http://twitter.com/Louisda16th

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asimut core dumps when there is a save in the pattern file
by Ashwith Rego 19 May '12

19 May '12

Hi, I was trying a structural simulation using asimut (I've attached the files in mux.tar). The files andg.vst, org.vst and invg.vst were generated by boog.I ran the following command: asimut mux mux_in mux_out The output I got is the following: ###----- processing pattern 0 : 0 ps -----### ###----- processing pattern 1 : 0 ps -----### ###----- processing pattern 2 : 0 ps -----### ###----- processing pattern 3 : 0 ps -----### ###----- processing pattern 4 : 0 ps -----### ###----- processing pattern 5 : 0 ps -----### ###----- processing pattern 6 : 0 ps -----### ###----- processing pattern 7 : 0 ps -----### ###----- processing pattern 8 : 0 ps -----### ###----- processing pattern 9 : 0 ps -----### ###----- processing pattern 10 : 0 ps -----### ###----- processing pattern 11 : 0 ps -----### ###----- processing pattern 12 : 0 ps -----### ###----- processing pattern 13 : 0 ps -----### ###----- processing pattern 14 : 0 ps -----### ###----- processing pattern 15 : 0 ps -----### Segmentation fault (core dumped) I'm not sure where would be the right place to report this so I thought I'd post it here. I also don't know where the core dump is located or what to do with it. I have generated a log file using the report feature in Fedora. That has been attached as asimut_err. Is there something I missed which caused the program to behave like this? The issue doesn't come up if I remove the save at the end. Thanks Ashwith J. Rego ----------------- My Webpage: http://ashwith.wordpress.com/ Find me on LinkedIn at: http://www.linkedin.com/in/ashwith Follow Me on Twitter at: http://twitter.com/Louisda16th

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Re: [free-electronic-lab] electronic-lab Digest, Vol 43, Issue 5
by liu 18 May '12

18 May '12

于 2012年05月18日 20:00, electronic-lab-request(a)lists.fedoraproject.org 写道: > gnucap and ngspice usage and feedback the ngspice simulation of large-scale circuit is very slow.Two NE555 circuit, the use of“ tran 10ms 10s” Command simulation takes about 10 minutes

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gnucap and ngspice usage and feedback
by Yusuf Matcheswala 17 May '12

17 May '12

If you have used gnucap and/or ngspice, what has been your experience with the usage of these tools for simulation especially of larger analog blocks regarding the tool's speed, accuracy, issues with convergence etc? I will appreciate the valuable feedback form this forum. Thanks,

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Xilinx System Generator Alternative
by Ashwith Rego 13 May '12

13 May '12

Hi, I have two questions. 1. Are there any alternatives to Xilinx's System generator? Possibly something that converts octave or scilab (preferably xcos) code to VHDL or Verilog. 2. What sort of support is available for SystemVerilog in FEL? Thanks Ashwith J. Rego ----------------- My Webpage: http://ashwith.wordpress.com/ Find me on LinkedIn at: http://www.linkedin.com/in/ashwith Follow Me on Twitter at: http://twitter.com/Louisda16th

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FEL added to easyfix
by Shakthi Kannan 04 May '12

04 May '12

Hi, I have added Fedora Electronic Lab Trac to easyfix: http://fedoraproject.org/easyfix/#fedora-electronic-lab If there is a particular task/ticket that is easy for newbies to get started with, one needs to add the word "easyfix" in the keyword section of the ticket, and it will show up at the above URL. Regards, SK -- Shakthi Kannan http://www.shakthimaan.com

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Help with installation
by Jose Carlos Garcia Diaz 04 May '12

04 May '12

I have serious problems with the live-cd just blows up in intalacion and not actual mind is wrong, someone can help me "Primero Muerto Antes de Dejar Algo Inconcluso" Jose Carlos Garcia Diaz My profiles: [image: Facebook] <http://www.facebook.com/chepecarlos> [image: WordPress] <http://alsw.wordpress.com/> [image: Twitter]<http://twitter.com/alswBlog> [image: devianArt] <http://chepecarlos.deviantart.com/> [image: Google Plus]<https://plus.google.com/107649588304660451493/> Contact me: [image: Google Talk] feliciachepe(a)gmail.com [image: Skype]carlos.garcia.expor [image: MSN] feliciachepe(a)hotmail.com [image: Google Talk] chepecarlos(a)alswblog.org Mis ultima aporte en ALSW(Anime y linux): Un css para vestidos gala :)<http://alswblog.org/2012/05/01/un-css-para-vestidos-gala/>

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electronic-lab May 2012